The testing of semiconductor devices is important to maintain high quality during their manufacture. The automatic test equipment (“ATE”) employed to carry out this task comprises sophisticated electronics capable of sending test signals to, and capturing output signals from, one or more devices under test (each, a “DUT”). ATE channel hardware, typically referred to as channels, orchestrate this back and forth flow of signals. These signals flow in the form of packets within a data stream which may be interchangeably referred to as “data packets” or “symbols” within this application.
FIG. 1 depicts conventional channel circuitry sending tester data signals originating from a pattern generator 100 to a DUT 102 via interface circuitry commonly referred to as pin electronics 104. The pin electronics circuitry 104 includes high-speed differential drivers and receivers to provide a communication interface between the tester and the DUT 102. Preferably, the drivers and receivers have available bandwidths of up to twelve Gbps, with unidirectional differential capabilities. Suitable drivers and receivers include those available from Agere Systems, Allentown, Pa. as models TMOD110, and TRCVO110g.
Response signals from the DUT 102 are captured and compared to expected data with the resulting comparison data transmitted to a failure processor 106 in order to determine whether the DUT 102 passed or failed the test. The expected data from the DUT and the drive data from the generator 100 are typically programmed in the pattern generator vector memory (not shown) to occur at precise times, in accordance with how the DUT 102 should behave. If the data captured from the DUT 102 fails to correspond with expected data, the DUT 102 is considered to have failed that aspect of the test.
Modern semiconductor devices are trending towards employing multiple processing cores on the same chip. Adding to this complexity is the overall trend towards implementing on-chip communication protocols. The end result is an exponential increase in the chip gate count, yet only modest increases in the available pin counts. Consequently, multiple sub-circuits often share the pin-interface.
FIG. 2 illustrates generally the shared interface scheme, where a plurality of DUT subcircuits (200a-200c, generally 200) send data packets to a DUT communications port 202. The communications port 202 serves as the gatekeeper to accessing the DUT output pin 204. Each of the subcircuits 200 may be clocked by a separate clock having a frequency different from not only the other subcircuits, but also possibly different from the communications port clock. An asynchronous arbitrator 206 handles the sequencing of the data packets to the DUT output pins 204.
FIGS. 3A and 3B illustrate shared interface problems inherent in the operation of traditional ATEs during evaluation of DUTs 102. These problems are generally characterized as “cycle slipping” and “out-of-order data” errors, and represent three distinct types of non-deterministic data (“NDD”). “Cycle slipping” often results from the communications port clock operating at a frequency different from that of the subcircuit clocks. The result may be that the DUT output pins 204 sees periods of idle data, or a number of cycles of non-packetized information. These idle periods may occur at the beginning of a data transmission (NDD Type 1), or between packets of data (NDD Type 2). In a situation involving cycle-slipping, the actual data may not show up at the originally expected cycle of tester operation, but yet still reflect acceptable device signal behavior.
Out-of-order data (NDD Type 3) often results from the subcircuits attempting to access the communications port 202 (FIG. 2) on the same clock edge, or having differing delays due to environmental conditions. FIG. 3B illustrates the general concept on how an expected sequence may be disturbed into an out-of-order packet sequence.
Two different protocols are used for communication with the DUT 102. These are a high speed serial (“HSS”) protocol and a parallel protocol. The challenges presented by HSS protocols are not identical to those presented by parallel protocols. With parallel protocols, it is possible to program a match loop to handle Type 1 NDD. A match loop is a mechanism that prevents the vector data from the generator 100 from advancing until an unexpected data vector occurs. With HSS protocols however, this isn't possible since the idle period of a bus has random synchronization packets inserted. Additionally, a parallel bus spreads all the bits associated with a single byte of a packet across all the data pins of a bus. Real time analysis of the received protocol must take into account all data pins before making any determination on whether that byte was appropriate or not. HSS busses handle the bits differently. Due to the encoding protocol and the serial nature of the bus, each byte is fully contained on a single lane or bus line.
Another challenge unique to HSS protocols is “running disparity non-determinism.” In an 8B/10B protocol, each 8-bit byte can be translated into 2 10-bit symbols. One of the goals of the transmitter in the ATE is to keep the number of 1s and 0s balanced in the data stream. Running disparity is the determination of whether more 1s have been transmitted in the last symbol (typically referred to as positive disparity), or more 0s have been transmitted (typically referred to as negative disparity). If the 1s and 0s are balanced, then running disparity remains unchanged. Non-determinism in the area of running disparity can be a side effect of one of the other types of non-determinism. An inserted packet, in the case of Type 3 non-determinism, can change the running disparity of the data as it is transmitted. In such an instance, this would cause functional failures to be identified by the ATE that should really be ignored. Therefore, any solutions for NDD transmissions for serial busses also need to take the running disparity into account.
Both “cycle slipping” and “out of order” data present unique challenges to ATEs. As previously described in the context of FIG. 1, traditional ATE relies on the comparison of expected data, at expected timings, to actual data and actual timings. Providing unknown and unexpected delay and data sequences in the actual DUT data for conventional ATE often results in post-test data descrambling to determine whether the device failed or passed. This may involve substantial modifications to the test program and create overhead in program development and test time.
Thus, a need exists for a system and method of detecting and correcting non-deterministic data that provides substantially real-time validation results and maximizes flexibility for the device manufacturer while reducing test costs.